LD-DDR-SDRM-C-0001-050

SDR/DDR-SDRAM Controller

1.1. GENERAL DESCRIPTION

SDRAM Controller is dedicated for MAC controller and processor accesses to a common SDRAM memory.
SDRAM Controller accepts any SDRAM device compliant with JDEC Standard N0 21-C, covering a large family of SDR-SDRAM or DDR-SDRAM.

1.2. FEATURES

controls two user interfaces, with MAC and processor, and a JDEC Standard N0 21-C interface with SDR/DDR SDRAM devices;

the SDRAM controller is fully programmable by a programmable access port. All access timing parameters such as CAS latency, row-to-column delay, refresh interval, etc., are programmable to support different speed of SDRAM devices and different operating frequencies. The timing parameters are set to the proper default values during initialization and can be modified during run-time.

width: user ports of 4 bytes, SDRAM device port of 2 bytes;

throughput of 4 bytes/cycle;

the controller can be programmed to support SDRAM sizes of 2/4/8 MB and 256/512 bytes per row;

high performance SDRAM controller designed for transferring data at the highest possible data rate by two ports based on the user requests:

MAC controller in full page burst mode, burst lengths is multiple of sectors, the size sector is variable;
processor in full page burst mode; 1x4, 8x4 bytes burst lengths for read and 1x4 bytes burst lengths for write;

the pipeline feature of the SDRAM controller allows:

the user to specify the next access address while the current data transfer is in progress with ability to interleave between banks in order to hide precharge and activation time of MAC access or processor access;
multiple data transfers from MAC can be cascaded together for access the SDRAM continuously (in sector burst mode), without any wasted cycle between accesses;
the MAC access port provides the means for stop the transfer (in middle of sector) and resume it when the data is available;
the processor accesses have high priority over MAC accesses. If a processor request arrives during a MAC access, the last is interrupted (either it is in stop/run state) without wasted cycle in switching between accesses (if they are in different blocks). So processor see the external memory as its proper memory without MAC interference.

the SDRAM controller keeps the previous accessed row open. The SDRAM controller simultaneously keeps track of four open rows, one for each bank. If the new request hits the same row, a column access is performed, eliminating row access time.

the user-friendly interfaces of the SDRAM controller permits the user to provides the begin address for each access and the SDRAM controller automatically generates the row (RAS) and column (CAS) access cycles to transfer data. In burst data transfer, zero wait state data bursting is supported to maximize memory bandwidth.

automatic refresh generation: the SDRAM controller periodically issues refresh commands. There is the possibility of cumulating of refresh requests in case of conflict with the user requests (up to 15 refresh requests) and service them later in back to back fashion.

all power saving modes, important for low power field, are implemented: self refresh, precharge stand-by, active stand-by, deep power-down.

Notes:

The SDRAM controller can be programmed to support:

Data width of SDRAM device interface of 16 or 32 bits;
SDRAM sizes over 8 MB;

A simplified version for SDR-SDRAM is available.

1.3. BLOCK DIAGRAM